\doxysection{C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+STM32\+H7xx\+\_\+\+HAL\+\_\+\+Driver/\+Src/stm32h7xx\+\_\+hal\+\_\+rcc.c File Reference}
\hypertarget{stm32h7xx__hal__rcc_8c}{}\label{stm32h7xx__hal__rcc_8c}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Src/stm32h7xx\_hal\_rcc.c@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Src/stm32h7xx\_hal\_rcc.c}}


RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral\+:  


{\ttfamily \#include "{}stm32h7xx\+\_\+hal.\+h"{}}\newline


\doxysubsection{Detailed Description}
RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral\+: 

\begin{DoxyAuthor}{Author}
MCD Application Team
\begin{DoxyItemize}
\item Initialization and de-\/initialization functions
\item Peripheral Control functions
\end{DoxyItemize}
\end{DoxyAuthor}
\begin{DoxyVerb}==============================================================================
                    ##### RCC specific features #####
==============================================================================
  [..]
    After reset the device is running from Internal High Speed oscillator
    (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except
    internal SRAM, Flash, JTAG and PWR
    (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
        all peripherals mapped on these buses are running at HSI speed.
    (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
    (+) All GPIOs are in analogue mode , except the JTAG pins which
        are assigned to be used for debug purpose.

  [..]
    Once the device started from reset, the user application has to:
    (+) Configure the clock source to be used to drive the System clock
        (if the application needs higher frequency/performance)
    (+) Configure the System clock frequency and Flash settings
    (+) Configure the AHB and APB buses pre-scalers
    (+) Enable the clock for the peripheral(s) to be used
    (+) Configure the clock kernel source(s) for peripherals which clocks are not
        derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R
        and RCC_D3CCIPR registers

                    ##### RCC Limitations #####
==============================================================================
  [..]
    A delay between an RCC peripheral clock enable and the effective peripheral
    enabling should be taken into account in order to manage the peripheral read/write
    from/to registers.
    (+) This delay depends on the peripheral mapping.
    (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
        after the clock enable bit is set on the hardware register
    (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
        after the clock enable bit is set on the hardware register

  [..]
    Implemented Workaround:
    (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
        inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
\end{DoxyVerb}


\begin{DoxyAttention}{Attention}

\end{DoxyAttention}
Copyright (c) 2017 STMicroelectronics. All rights reserved.

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-\/\+IS. 